Laboratoire de Cristallographie, Résonance Magnétique et Modélisations

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Noreddine KACHKACHI

Noreddine KACHKACHI
Fonction(s) : Ingénieur de recherche
Equipe(s) : RMN
Téléphone : 03 72 74 52 57
Service : Électronique

Experienced Microelectronics Design Engineer with 20 years of experience in designing, verifying and validating innovative digital IPs and Embedded Systems.

I worked in a large application domain containing video, signal processing, interfacing IPs for digital TV, Smart phone, defense, consumer ASICs and FPGA.

Expert in Front-End Digital EDA and Front-End Digital IC design, I went through the whole ASIC and FPGA design process from specification to Layout passing by functional verification and Logic/Physical Synthesis as well as Static Timing Analysis. I used cutting edge EDA tools and methodologies. Extensive knowledge of the Design Flow consolidated with Embedded Systems architecture, PCB Design and NMR/NQR instrumentation FPGA based design.

My major research activity, which aims to enhance the sensitivity of NQR/NMR instrumentation, is focused on two axes, the first one is FPGA design and validation as well as system design dedicated to the development of innovative and original NQR/NMR portable and miniaturized spectrometers.

The developed systems, hence embark digital and analog electronics as well as embedded software targeted to the detection and processing of weak RF signals especially for NQR technique .

In this context, I did the FPGA design, the embedded software design/upgrade, the system integration, the functional verification, the stand alone and system validation of an FPGA based compact NQR spectrometer.

My second research axis is the definition and implementation on SW or on digital hardware target (FPGA) of NQR/NMR de-noising techniques like SVD, digital filtering, NMR per-processings,…
The NQR technique, though it suffers from weak sensitivity, has a wide spectrum of possible applications like drugs analysis and counterfeits detection, narcotic detection, operator-secure explosive detection, and molecular structures studies.

The obtained results so far are very satisfying since, using the developed systems, we easily detected the expected frequencies for reference samples as well as for commercial ones (e.g. Commercial and lab synthesized Paracetamol) .

The SNR of the system was also significantly enhanced compared to old systems (x10 thanks to refurbishing and new acquisition using oversampling and then x2,5 thanks to FPGA design and integration).

In order to achieve these developments I brought up my expertise in FPGA/ASIC IC (Integrated Circuit) Digital Design coupled with my skills in embedded and PCB design. This expertise was accumulated during my past years in in microelectronics industry (ST-Microelectronics, Amesys, Cadence,…) in which I achieved the design and validation with first silicon success of several IPs and systems.

Education :

1994-1997 : Classes préparatoires (Math Sup et Math Spé) au lycée Moulay Youssef (Rabat)
1997-2001 : École Mohammedia des Ingénieurs (Rabat), (Premier de l’option électronique et télécommunications)
2001 : Stage ingénieur à ST-Microelectronics (Grenoble)
2001 : Diplôme d’ingénieur d’état en électronique et télécommunications (EMI)
depuis 2019 : Préparation d’un doctorat intitulé «Amélioration de la sensibilité de l’instrumentation en spectroscopie de Résonance Nucléaire» dirigé par Pr. H. Rabah de l’IJL et codirigé par Dr. A. Gansmuller du CRM2

Professional carrier :

Since 2015 :
Research Engineer CNRS (Nancy) : (Permanent position)
FPGA design, system design and validation of compact NQR spectrometer
Technologies: {VIVADO, SDK, Embedded Linux, Zynq AP SOC, RF preamplifiers/Amplifiers, IQ Modulation/Demodulation, ADCs, NMR, NQR, General Electronics}.

2013 – 2014 Cadence :
Lead Application Engineer (Munich) :(Permanent position)
-Pre-sales campaigns and customer support on Cadence tools (Front-End Digital Design)
-Customer education on High Speed and Low Power intended design techniques

Technologies: {IUS, RTL Compiler, Encounter Conformal , Encounter EDI, DFT, CPF Low Power flow}.

2010-2013 MASCIR :
Senior Embedded Systems Engineer (Rabat): (Permanent position)
Architecture enhancement, PCB design, FPGA design and validation of complete embedded system (HDI Boards + FPGA+ hundreds of SMT components) : CMOS/CCD Micro-camera HD video quality demonstrator
Technologies: {VHDL, FPGA, Altera Cyclone II & III, Micro-Camera, PCB Design}.

2008 -2009 Amesys :
Senior FPGA Design Engineer (Rabat/Aix-En-Provence) (Permanent position)
FPGA Design and verification of an RF spectrum analyzer
Technologies: {VHDL, FPGA, DSP, Modelsim, Functional verification, Xilinx Virtex 5}.

2007 -2008 EASII-IC :
Senior ASIC Design Consultant (Nice(Permanent position)
ASIC Design Consultant at Texas Instruments
Technologies: {DFT, ASIC Front-end digital Design}.

2001-2007 : ST-Microelectronics :
Senior ASIC Front-End Digital Design Engineer (Rabat/Grenoble) (Permanent position)
Actively contributed to the development of several Digital TV Decoders and Application Processors (STV3550)
(Digital Video Output Stage) , STV3600, STV2310(Video Scaler), Nomadik(Host Port Interface), …)

Technologies: {VHDL, ASIC, Specification, RTL testbench, Synchronous Digital Design, Methodology, AVP(Architectural Verification pattern), Simulation (Cadence Ncsim), Logic Synthesis (Synopsis Design Compiler), STA (Synopsis Primetime)}.

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